1. Technical Field
The invention relates to communications network protocols. More particularly, the invention relates to initialization protocols for communications networks that have a ring topology.
2. Description of the Prior Art
The next generation of CPUs will bring with it a significant increase in both instruction level parallelism and clock frequency. The system infrastructure that supports these processors must therefore supply much higher I/O and main memory bandwidths than are presently available. Such CPUs must also exploit a considerably greater degree of parallelism in accessing main memory, to compensate for the increasing imbalance between processor speed and memory latency, thereby also driving up main memory bandwidth requirements. It is thus unlikely that the needs of even moderately demanding applications--commercial or technical--will be satisfied by bus-based solutions in this time frame.
Consequently, much attention is being given to ring networks as the next best hope for solving the bandwidth problem. A ring topology is inherently a communications network topology where all nodes are equal in connectivity. FIG. 1 is a block level schematic diagram of a typical ring configuration 10 in which several processors 11-14 and memory modules 15-17 appear as individual nodes on a network ring 18.
One problem associated with a ring network is that of ring initialization. Ring initialization using the fewest number of device package pins is difficult, but necessary because the device package is often the most expensive portion of the device and adding pins to the device package adds significantly to the device cost. Overhead associated with ring initialization ideally should have minimal impact on the implementation and packaging cost of a ring system.
It is possible to place several copies of the boot code used for initialization in the system, for example, one on each bus. This, however, adds unnecessarily to the final system cost. In addition, if the boot code also has a portion of non-volatile memory functionality present, then there is the problem that there may be the architectural appearance of more than one copy of boot code in the system.
If the processor contains the boot code and non-volatile memory, then for a uniprocessor implementation, there is a very simple known mechanism for fetching and executing the boot code and performing non-volatile memory loads and stores. However, in a multiprocessor system, there is a difficulty that the other processors must locate the processor containing the boot code and send instruction fetches to that processor. That processor must then respond to those instruction fetches.
Additionally, in a multiprocessor configuration, a processor associated with each node, containing a CPU and a bus, must be sufficiently initialized to forward and return instruction fetches. Placing the initialization boot code on one such processor implies that the one given processor bus has an almost direct connection to the boot memory interface. Other processors, however, must also be able to send instruction fetches into the ring.
The anticipated benefits of a ring topology are straightforward. Because each electrical connection is point-to-point, much higher signal rates, and thus more bandwidth per pin, can be achieved. Because the system clock is propagated along with the data, along matched paths, only the relative skew between signals must be managed, and not the sum total of skew and propagation delay between devices. This too may contribute to higher clock rates, and should remove some of the need for very tight packaging geometries required when bus-based solutions are pushed to their limit.
In view of the many merits of a ring network, it would be advantageous to optimize all aspects of the ring architecture. It would therefore be advantageous to provide a fast and reliable, low overhead ring initialization scheme.